STMicroelectronics Invests $60M in Tours, France for Advanced PLP Technology

Tours Becomes Hub for ST’s Advanced PLP Technology with $60M Investment

STMicroelectronics has revealed new details about the growth of the next generation of Panel-Level Packaging (PLP) technology, having finished a pilot line at its Tours site in France, which is expected to be operational in the third quarter of 2026.

PLP is a progressive, automated chip packing and test process technology that carries increased engineering efficacy and reduces costs, and is a main enabler for generating the next generation of smaller, more powerful, and cost-effective electronic devices. The large-area transporter in PLP (large rectangular shapes in place of circular wafers) enables higher engineering throughput, making it a more effective solution for high-volume manufacture. Building on its first-generation PLP line in action in Malaysia and its worldwide technology R&D network, ST aims to grow the next generation of its PLP technology to preserve its technological leadership and expand the use of PLP across various ST products for automotive, manufacturing, and customer applications.

“The growth of our PLP competences in our Tours site is designed to proceed this advanced approach to chip packing and test engineering technology, improving efficacy and flexibility so it can be rolled out across an extensive portfolio of applications, comprising RF, analog, power, and microcontrollers. A multidisciplinary team of specialists in engineering automation, process engineering, data science and analytics, as well as skill and product R&D, will cooperate on this program, which is a main part of a larger planned initiative attentive on varied incorporation of a scalable, effective new tactic to chip addition,” expressed Fabio Gualandris, President Quality, Manufacturing and Technology of STMicroelectronics.

“With our fab in Malta, ST has previously established its competence to offer high-execution chip packing and test in Europe. As we redesign our worldwide engineering footprint, this new initiative in Tours will expand our process, design, and engineering invention abilities, helping the growth of next-generation chips in Europe.”

The growth of the new PLP pilot line in Tours is supported by a capital investment of around $60 million, which has already been allocated as part of the company-wide program to redesign the company’s engineering footprint. Further synergies are anticipated with the local R&D ecosystem, which includes the CERTEM R&D center. As previously declared, this program emphasizes progressive engineering substructure and redefined missions for certain locations in France and Italy to support their long-term success.