In July 2026, the semiconductor industry in the era of AI is moving past the pattern of relying on single and massive chips. Advanced packaging is known as the essential craft of interconnecting multiple specialized chips together. The procedure helps the chips to function as a single, powerful unit that helps to massively handle the workload of the future.
Intel has been in this industry for decades and has been handling chip packaging for years in the U.S. and across the globe. It’s one of the most crucial parts of creating multi-chip packages for today’s technology products.
Inside Intel's Rio Rancho, New Mexico facilities, advanced packaging technologies are expanding the "reticle limit" scaling packages to 8x the industry standard today, and over 12x by 2028.
We’ve moved past the era of one big chip to a system of chips, almost like a “silicon mosaic”, where specialized tiles are interconnected in a single, massive package.
“Back in the 1980s, this site was the leader in 6-inch wafer manufacturing. Now over 40 years later, things have flipped, and this site is the leader in the United States for advanced packaging,” explains Katie Prouty, manager of Intel’s Fab 9 advanced packaging facility in New Mexico.
To meet the growing demands of AI, the technology brand is pushing the boundaries of physically possible situations. Intel Foundry is building up with Foveros stacking and across with EMIB interconnects.
“Some of the customers are coming to us first for advanced packaging,” Prouty says. “When we’re successful in delivering to those customers, they’ll continue to grow their trust and faith in Intel as a foundry.”
What started in Rio Rancho, New Mexico, as 25 employees in 1980, has now proudly grown to 2,700 employees and 500 suppliers, bringing critical U.S. advanced packaging technology to market.
One of the advanced packaging processes happening at Intel’s New Mexico Fab 9 majorly focuses on connecting smaller specialized chip tiles, or chiplets, into a single, high-performance system. The Foveros technology allows Intel Foundry to connect such chiplets on a silicon interposer.
“Inside the fab, the chip attach tool is the first step in Intel’s Foveros advanced packaging process,” says Chris Seibert, Principal Engineer at New Mexico’s Fab 9. “If we use a food analogy, this is the tool that brings in a ‘pizza crust’, or silicon wafer, and whatever ‘pizza toppings’ or specialized chiplets you want, we feed into the other side of this machine, and it attaches them to the top of that ‘crust’.”
The next procedure involves the use of a different tool that looks like an oven to bake the system together. Once it comes out, the overhead robot track system of FOUPs (front-opening unified pods) brings the wafer to another machine where epoxy fills in under and around those chiplets to make sure everything is pressed together. Then the wafers are diced into individual packaging in another tool with the help of water-cooled blades for precision. “The great part about that process is it lets us take a bunch of different chips from different designs or different technology nodes and put them all together onto one wafer,” Seibert says.
With the help of Foveros technology, individual chiplets function as a single, powerful unit that runs faster while handling massive workloads. It also helps laptop batteries to last longer by placing power-hungry circuits on more power-efficient process nodes. Hence, laptops are now available in thinner models, and edge computing devices can now fit into smaller spaces without any changes in performance. It also allows for more features to be packed into a smaller footprint, from the factory floor to your desk.
The advanced packaging process of semiconductors includes a technology called EMIB (Embedded Multi-die Interconnect Bridge), where specialized chips are linked together on a package with tiny silicon bridges embedded in the substrate. The approach also allows different chips to work together as a single unit, providing the massive power needed for AI, along with improving efficiency and reducing manufacturing costs.
While other foundries might use expensive silicon interposers as the connection layer between chips, Intel Foundry embeds tiny, high-speed silicon bridges only where they’re needed. It’s a data shortcut that slashes costs and turns this “silicon mosaic” of chiplets into an AI powerhouse.
For example, when you have complex data center products with multiple chips next to each other, EMIB creates a bridge in the substrate so they can talk to each other without a large wafer-based interposer.
In 2026, the latest development is EMIB-T, which adds channels through that bridge to deliver power directly to the chips, instead of around it, along with improving efficiency and signal routing required by the latest high-bandwidth memory (HBM) technologies. It’s more than speed; it is freedom. Only Intel Foundry can mix and match chiplets from different sources directly onto the industry’s largest substrates. That flexibility is how we can support the next generation of AI engines that run data centers.
10 August 2026
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