Taiyo Holdings Co., Ltd., based in Tokyo, presented a paper, co-authored with imec, which is one of the world’s biggest semiconductor research institutions, at the 14th IEEE CPMT Symposium Japan, concentrating on the “FPIM (TM) Series”, a negative-type photosensitive protecting material for fine-pitch RDLs planned for the damascene procedure, developed as an upcoming-generation semiconductor-packaging resource.
The RDL is a significant technology in the most advanced semiconductor packaging for more effective electrical networks, and it is currently produced primarily through the semi-additive process (SAP). The damascene process, imec suggests, will become important for forming interconnects with line spacing of 1.6 micrometers or less in the future, as finer wiring is pursued. In reply, Taiyo Holdings has been emerging this resourcing as a next-generation fine-pitch RDL resource for the damascene procedure and has been conducting joint research with imec since October 2022.
In this research, a three-layer RDL structure was fabricated on a 12-inch wafer using this resource, and estimates were performed. Each wiring pitch attained the target dimensions as follows: CD 1.6 micrometers for the RDL1 coating on the wafer, CD 2.0 micrometers (with a via center-to-center pitch of CD 4.0 micrometers) for the via layer, and CD 1.6 micrometers for the RDL2 coating. These values are extremely close to the resolution limit of the low-NA stepper used in this study.
The estimation results for the electrical features, specifically leakage current and barrier, of the RDL1 layer with a 1.6 µm CD were favorable. As a result of this joint study with imec, it was established that this resource possesses superior electrical properties, high resolution, and quality, making it well-suited for use in the CMP procedure. In the future, the corporation focuses on creating RDLs on wafers with a wiring pitch of CD 500 nm or less, while continuing to verify the long-term performance of electrical characteristics and reliability.
Taiyo Holdings will continue developing resources that advance the semiconductor-packaging field, including further performance improvements for AI semiconductors. In addition, transportation of small-quantity samples of this resource for R&D purposes started in 2025.
26 January 2026
26 January 2026
23 January 2026
23 January 2026