Toshiba Boosts MOSFET Efficiency with New SOP Advance (E) Packaging

Toshiba has launched two new N-channel power MOSFETs, PM1R908QM and TPM7R10CQ5, using advanced SOP Advance (E) packaging to improve efficiency, reduce power loss, and lower thermal resistance for high-performance applications like data centers.

Author: Vidyesh Swar Published Date: 21 August 2025
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Toshiba Improves MOSFET Performance with Advanced Packaging

Toshiba Boosts MOSFET Efficiency with New SOP Advance (E) Packaging

Image Credits: BISinfotech

Toshiba, a leading Japanese multinational company, has introduced two N-channel power MOSFETs featuring the company's latest packaging technology, SOP Advance (E). The adoption of the device is aimed at achieving higher efficiency, lower loss, and decreased thermal strain for data centers.

PM1R908QM and TPM7R10CQ5 are the two main devices, where TPM is an 80V-rated power MOSFET with a drain-source on resistance, which supports drain current up to 238 A at a case temperature of 25 °C. The device also supports a fast switching profile with a typical rise and fall time. It offers maximum RDS, where it enables fast reserve recovery time of 45 ns and a low reverse recovery charge of 43ns. The major reason behind the adoption of these specifications is that they further help in synchronous rectifications.

Moreover, both devices fit under the same compact SOP Advance(E) footprint of 4.9mm x 6.1mm, which helps in saving space for electronic devices.

The semiconductor also influences the power efficiency of the MOSFET, which acts as a major contributor in these applications like such as frequency switching and densities. Old packaging methods create extra resistance and heating issues, especially when chips need to work at high speed and high power.

The SOP Advance (E) format also works on various challenges with an internal availability to redesign the layout and improve the thermal conduction path.

Toshiba mentioned that the result has been impactful, where 65% and 15% reductions in package and thermal resistance as compared to the traditional method.

The thermal resistance decreases the delays in saturation under load, and the packaging resistance directly reduces conduction losses. The rising advancements in these packages have led to the maximum operating channel temperature of 175 °C for both devices.

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